The subject of the invention is a digital system for computing of the values of composite arithmetic expressions of numbers in a binary system, designed in particular for computing of the values of polynominal expressions ##EQU2## X.sub.IJ, ESPECIALLY OF THOSE WITH BIG VALUES OF N AND WITH NUMBERS X.sub.IJ POSSESSING MANY SIGNIFICANT BITS. The system is mainly designed for use in large computer and computers systems, especially in specialized high-speed processors for numerical computations and in other high-speed digital systems performing arithmetic operations. The system may also be used for simultaneous computations of several independent arithmetic expressions as well as for the multitask collisionfree work with several different computers
In the known designs of electronic digital systems, the computation of composite arithmetic expressions usually amounts to performing successive arithmetic operations, the results of which being, in turn, the arguments of successive operations of these expressions until a final result is obtained. Fairly well known are electronic devices and digital systems for fast performance of multiplications and additions. These operations are the basic ones when computing the values of many arithmetic expressions, and particularly polynomial ones ##EQU3## X.sub.IJ. In this case, the speed of multiplication is most important for this operation is far more time-consuming than addition. There exist many digital systems suited to a pipeline processing of information, ensuring very high effective speed of information processing and especially very fast execution of long sequences of multiplications and additions. In previously known electronic digital systems for very fast multiplication of two binary numbers, all partial products, necessary to obtain the final product, assigned to successive groups of multiplier bits, are simultaneously added in parallel to one another. In the multiplying system of 48-bit numbers, where the individual partial products are attributed to the pairs of successive multiplier bits, 24 such products are added simultaneously. The digital system performing this operation consists of 22 carry-save adders and 1 carry propagation adder. The above mentioned adders are connected together in a multilayer cascade, containing in seven layers respectively 8, 5, 3, 2, 2, 1, 1, carry-save adders and in the 8th layer -- carry propagation adder. All these adders form one switching network and do not contain storing elements. The time of performing the addition of 24 partial products in such a system of adders is the sum or the maximum time of propagation of signals through 7 one-position adders connected in series and the time of propagation through 1 carry propagation adder with approximately 90 positions; the latter adder contains complex carry-skip circuits for minimization of the maximum time of carry propagation. Partial products being added in the described set of adders represent the multiples of multiplicand shifted with respect to one another, assigned to the pairs of multiplier bits representing the integers from 0 to 3. To avoid the time-consuming determination of three-fold multiplicand, which requires an extra addition of the multiplicant and the shifted multiplicant, the presented multiplication system contains a switching network which transforms the multiplier in parallel. Output signals of this network, assigned to the successive groups of multiplier bits, represent the numbers -2,- 1,0,1,2, instead of the numbers 0,1,2,3. In the described multiplication system, the double multiplicant is obtained by shifting the multiplicand by one bit position to the left, and the negative multiples of the multiplicand -- by negating the bits of the positive multiples and the addition of correcting "one" in the least significant binary position. The multiplying system containing the described set of adders has been described in the following papers: C. S. Wallace "A Suggestion for a Fast Multiplier", The Institute of Electrical and Electronics Engineers, Transactions on Electronic Computers, volume Ec-12, pages 14-17, February 1964; T. G. Hallin, M. J. Flynn "Pipelining of Arithmetic Functions", The Institute of Electrical and Electronics Engineers, Transactions on Electronic Computers, volume EC-21, pages 880-886, August 1972; J. W. Gawrilow, A.N.Puczko "Arifmeticzeskije ustroistwa bystrodiejstwujuszczich elektronnych cifrowych wyczislitielnych maszin" /Arithmometers of Fast Electronic Computers/ -- Publ. "Soviet Radio", Moscow 1970, pages 133-180; and carry, skip circuits, also named carry, look-ahead circuits, in the paper: O. L. MacSorley "High Speed Arithmetic in Binary Computers", Proceedings of the Institute of Radio Engineers, volume 49, No. 1, 1961, pages 67-91. In the previously used computers and digital systems, having the structure suited to the pipeline processing of information, the individual layers of switching networks, processing the information, are separated from each other by the layers of registers to provide gradual performing of the parts of different operations at the same time in different individual layers of the switching networks. Processing the successive information being performed in the individual layers of such computers and systems with constant frequency, depends upon the maximum delay of the layer. The pipeline processing of information has been described, among others, in the papers: M. J. Flynn "Pipelining of Arithmetic Functions", The Institute of Electrical Engineers, Transactions on Electronic Computers, volume EC-21, pages 880-886, August 1972; T. C. Chen et al. "Introduction to Computer Architecture", chapter 9, page 417, Publ. Science Research Associates, Chicago, USA, 1975.
A drawback of the known computers and digital systems, particularly those intended to perform composite computations of great accuracy, is a relatively long time of executing the individual multiplications and additions. Even in the case of very fast adders, a considerably part of this time is consumed by the carry propagation. The carry propagation time, being the time of delay in numerous operations performed while computing of composite arithmetic expressions, has a considerable influence upon the total time of computation.
The aim of the present invention is to remove this drawback and to eliminate, as much as possible, all such information processing, including which have a character of series processes, carry propagation processes, which the end operations of multiplication and addition.